NASA is Using RISC-V Vector Spec to Soup Up Space Computers

With the growing demand for applications that require multiple cores and AI, ML, and computer vision capabilities, faster and power-efficient processing is essential. At the same time, companies are looking to simplify design cycles with more portability and re-use, broader extensibility, and more design scalability. The RISC-V Vector spec (RVV) version 1.0, ratified by RISC-V International last December, was created to meet these market requirements and make it easy to implement vector instructions for modern workloads.

Several companies, including SiFive, have solutions already in the market to address the challenges designers face in implementing vector technology.

RISC-V Vector spec benefits 

In terms of code size, performance, and area, RVV offers a powerful and extremely efficient alternative to packed-SIMD and GPUs, which are very inefficient for processing large datasets. One problem with packed-SIMD and GPU implementations is that they can require multiple new instructions, so the chip size increases every time new data types are introduced. Additional code is also often required for applications that have specific requirements, increasing code size, and bill of materials costs, along with consuming more power.

With just a few hundred instructions in the Vector ISA, RVV is much smaller than typical packed-SIMD alternatives. Since RVV is so small, it reduces the area that is required for compiled software (the compilers generate very dense code), enabling designs to have better power efficiency and a smaller memory footprint. The good news is code designed and written for packed-SIMD implementations can be easily ported to RISC-V vectors for a seamless transition.

Another benefit of RVV is that it’s vector length agnostic, so software written for a RISC-V vector processor is compatible with other vector processors. This means that a product designed for a 256-bit length vector register processor will also work with a longer vector register length processor, such as a 512-bit solution.

This approach gives developers the freedom to choose what vector size offers the ideal balance of performance, power, and area for specific application workloads. Additionally, being able to use the same software for many different vector processors saves development time, allowing companies to get their products to market faster.

RVV further reduces software complexity by allowing developers to consolidate custom DSP functionality into a vector processor, streamlining development while still achieving performance and efficiency goals. This feature is becoming more important as companies are increasingly using one or more separate custom DSPs to perform specific application tasks.

A few other key advantages of RVV: it’s a great compiler target; RVV supports both implicit auto-vectorization and explicit programming models; and RVV works with virtualization layers. Additionally, RVV fits into standard fixed 32-bit encoding space and offers an ideal base for future vector extensions (allowing for even greater customization).

RVV works with low-cost designs, as well as extremely high-performance applications, since the specification supports in-order, decoupled, or out-of-order microarchitectures, in addition to integer, fixed-point, and/or floating-point data types. These data types are all efficiently executed on the same single vector arithmetic logic unit to simplify the processor architecture, which improves power efficiency and reduces chip area.

NASA HPSC processor

One especially notable implementation of RVV is NASA’s next generation High-Performance Spaceflight Computing (HPSC) processor.

HPSC will utilize SiFive Intelligence X280 RISC-V vector cores (which support RVV extensions), as well as additional SiFive RISC-V cores, to deliver 100× the computational capability of today’s space computers. The RVV extensions allow the X280 to support extremely high-throughput, single-thread performance, while also managing significant power constraints. NASA’s HPSC will be used for future Mars surface missions and human lunar missions, along with applications including industrial automation and edge computing for other government agencies.

Building on an open standard, a lot of the code written for RISC-V vectors will be readily available in the fast-growing RISC-V ecosystem for developers. There are also a full range of open source and commercial tools for compilation, modeling, debugging, and tracing. These design tools help reduce development costs and accelerate products to market.

All in all, RVV offers an ideal vector processing approach to meet the growing demand for data heavy operations such as ML inference for audio, vision, and voice processing. RISC-V vector processors are already being used for a broad range of applications ranging from computer vision, mobile ISP, and edge AI to datacenter AI, and will continue to see explosive market adoption in the coming years.

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